FPGA Dynamic Partial Reconfiguration work flow

Product life span, power consumption and flexibility are key factor in many scenarios as avionics, military, transportation, etc. Nowadays the FPGA is one of most used electronic devices, thanks to its flexibility and its relative low price. By an FPGA is possible to increase drastically the design flexibility and extend the product life span as well. Although, the FPGA is reconfigurable device the market is pushing the FPGA technology further beyond the edge. A new concept of reconfiguration has been introduced by Xilinx. PDR (Partial Dynamic Reconfiguration) is a run time reconfiguration mechanism that allows to meet critical constraint such time to reconfiguration, power consumption and adaptive hardware. PDR allows to partial reconfigure the FPGA on fly, the FPGA will remain in operation while the others sub-area is being reconfigured.

Edizione 2012 nella track Workshop.

Video di presentazione


60 minuti
FPGA RT application